Arora V 15K FPGA Programming and Configuration Guide
Comprehensive guide for programming and configuring Gowin Arora V 15K FPGA products, covering various configuration modes, interfaces, security features, and multi-boot processes.
Table of contents
Product Overview
The Gowin Arora V 15K FPGA series are high-performance devices based on SRAM technology. Because they are SRAM-based, these devices lose configuration data upon power-off and require reconfiguration after each power-up cycle. This guide provides detailed instructions on the various methods available for programming and configuring these FPGAs.
Configuration Modes
The Arora V 15K supports multiple configuration interfaces to suit different system requirements:
- JTAG: Conforms to IEEE1532 and IEEE1149.1 standards, ideal for development and debugging.
- MSPI (Master SPI): The FPGA acts as a master, automatically reading bitstream data from an external SPI Flash.
- SSPI (Slave SPI): The FPGA acts as a slave, receiving configuration data from an external host via an SPI interface.
- Slave SERIAL: A low-pin-count interface for serial configuration.
- Slave CPU: Supports 8-bit or 16-bit parallel interfaces for high-speed configuration.
Configuration Sequence and Safety
Upon power-up, the device undergoes a Power-On Reset (POR) sequence, followed by initialization, configuration, and finally entering User Mode. Security is a critical aspect of the design; the Gowin software incorporates CRC checks to ensure data integrity during transmission. Additionally, the devices support AES-128 bitstream encryption to protect intellectual property. Once the security bit is set, readback of the configuration data is disabled.
Multi-Boot and Remote Upgrades
The Arora V 15K supports flexible dynamic configuration through the Multi-Boot feature, which is available in Master SPI mode. This allows the device to store multiple bitstream images in Flash memory. If a configuration error occurs, the device can automatically fall back to a predefined Golden Bitstream, ensuring system reliability. Remote upgrades are also supported, allowing users to update the FPGA logic in the field without physical access.
Maintenance and Troubleshooting
The device includes an internal Status Register that is invaluable for debugging. By reading this register, users can determine the cause of configuration failures, such as CRC errors, timeout errors, or ID validation mismatches. Proper pin management, including the use of pull-up/pull-down resistors on configuration pins, is essential for stable operation. When configuration pins are reused as GPIOs, users must ensure that the external connection state does not interfere with the configuration process.
