BIOS and Kernel Developer's Guide for AMD Family 15h Models 60h-6Fh Processors

Quick guide for developers

This document serves as the BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 60h-6Fh processors. It provides the necessary technical specifications for BIOS engineers and kernel developers to interface with the processor, manage power states, and handle system initialization.

Processor Initialization

The initialization process is critical for system stability. Key aspects include:

• BSC Initialization: The Bootstrap Processor (BSC) must be initialized according to specific sequences.
• AP Initialization: Application Processors (AP) require distinct initialization steps.
• L2 Cache Usage: The L2 cache can be utilized as general storage during the boot process.

Power Management

The guide details advanced power management features to optimize efficiency:

• Processor Power Planes: Information on Serial VID (SVI2) interface features and voltage control.
• Core P-states: Defines performance states, including naming, numbering, and transition sequences after warm resets.
• Core C-states: Covers idle states (CC1, CC6, PC6), cache flushing, and C-state request interfaces.
• NB Power Management: Details on Northbridge P-states and transitions.
• Application Power Management (APM): Includes Core Performance Boost (CPB) and thermal limiting.

System Architecture and Configuration

Developers should refer to the following sections for system integration:

• Core Architecture: Details on compute units, TLBs, and virtual/physical address spaces.
• Interrupt Handling: Comprehensive guide to the Local APIC, including detection, register space, and interrupt delivery modes.
• System Management Mode (SMM): Covers SMM overview, operating modes, SMI sources, and locking mechanisms.
• Performance Monitoring: Instructions for using Core and NB performance monitor counters and Instruction Based Sampling (IBS).
• Configuration Space: Requirements for MMIO configuration coding and ordering.